There is a current interest in CMOS active pixel imagers for use as low cost imaging devices. FIG. 1 shows signal processing system 100 that includes a CMOS active pixel sensor (“APS”) pixel array 230 and a controller 232 that provides timing and control signals to enable the reading out of signals stored in the pixels in a manner commonly known to those skilled in the art. Exemplary arrays have dimensions of M×N pixels, with the size of the array 230 depending on a particular application. The imager pixels are readout a row at a time using a column parallel readout architecture. The controller 232 selects a particular row of pixels in the array 230 by controlling the operation of row addressing circuit 234 and row drivers 240. Charge signals stored in the selected row of pixels are provided on column lines 170 (see FIG. 2) to a readout circuit 242 in the manner described above. The pixel signal read from each of the columns is then readout sequentially using a column addressing circuit 244.
FIG. 2 shows a portion of the system 100 of FIG. 1 in greater detail. Each array column 349 includes multiple rows of pixels 350. Signals from the pixels 350 in a particular column 349 are readout to readout circuit 242. Generally, each column 349 of pixels is readout to an associated analog-to-digital block, which includes an analog-to-digital converter (“ADC”) 361 and a memory storage location 363. Alternatively, the pixel outputs on the columns are sequentially supplied to one analog-to-digital block having an associated memory for storing digital pixel signals. Typically, the digital values provided by the analog-to-digital converter 361 are twelve bit values. The results of the signal conversion to digital form are stored, temporarily, in a storage location 363 associated with the analog-to-digital converter 361. The digital signals are subsequently readout of the storage locations 363 and processed downstream of the readout circuit 242.
Typically, a readout circuit 242 includes other circuitry, although not shown in FIG. 2. For example, a sample and hold circuit is coupled between a column 349 and its associated ADC 361. Additionally, a gain circuit, or several gain circuits, may be coupled between a column 349 and its associated ADC 361.
A storage location 363, typically a RAM or DRAM memory (also referred to as the RAM block or core), is a substantial part of an analog-to-digital processing block. As there exists an ever increasing desire to reduce the size of electronic imaging circuits, it is desirable to reduce the size of the analog-to-digital block. As there also exists the desire to increase the speed of electronic imaging circuits, it is also desirable to increase the processing speed of the read out circuit.